flexible & versatile pci express ? switch features ? pex 8524v general features o 24-lane pci express switch - integrated serdes o up to six configurable ports o 35mm x35mm, 680 pin pbga package o typical power: 5.7 watts ? pex 8524v key features o standard compliant - pci express base specification, r1.1 o high performance - non-blocking switch fabric - full line rate on all ports o non-transparent bridging - configurable non- transparent port for multi-host or intelligent i/o support o flexible configuration - six highly flexible & configurable ports (x1, x2, x4, x8, or x16) - configurable with strapping pins, eeprom, or host software - lane and polarity reversal o pci express power management - link power management states: l0, l0s, l1, l2/l3 ready, and l3 - device states: d0 and d3hot o quality of service (qos) - two virtual channels per port - eight traffic classes per port - fixed and round-robin virtual channel port arbitration o reliability, availability, serviceability - 6 standard hot-plug controllers - upstream port as hot-plug client - transaction layer end-to-end crc - poison bit - advanced error reporting - lane status bits and gpo available - per port performance monitoring ? average packet size ? number of packets ? crc errors and more - jtag boundary scan multi-purpose, feature rich expresslane? pci express switch the expresslane pex 8524v device offers pci express switching capability enabling users to add scalable high bandwidth, non-blocking interconnection to a wide variety of applications including servers, storage systems, communications platforms, blade servers, and embedded-control products . the pex 8524v is well suited for fan-out , aggregation, dual-graphics, peer-to-peer, and intelligent i/o module applications. highly flexible port configurations the expresslane pex 8524v offers highly configurable ports. there are a maximum of 6 ports that can be configured to any legal width from x1 to x16, in any combination to support your specific bandwidth needs. the ports can be configured for symmetric (each port having the same lane width and traffic load) or asymmetric (ports having different lane widths) traffic. in the event of asymmetric traffic, the pex 8524v features a flexible central packet memory that allocates a memory buffer for each port as required by the application or endpoint. this buffer allocation along with the device's flexible packet flow control minimizes bottlenecks when the upstream and aggregated downstream bandwidths do not match (are asymmetric). any of the ports can be designated as the upstream port, which can be changed dynamically. end-to-end packet integrity the pex 8524v provides end-to-end crc protection (ecrc) and poison bit support to enable designs that require end-to-end data integrity . these features are optional in the pci express specification, but plx provides them across its entire expresslane switch product line. non-transparent ?bridging? in a pci express switch the expresslane pex 8524v product supports full non-transparent bridging (ntb) functionality to allow implementation of multi-host systems and intelligent i/o modules in communications , storage , blade server, and graphics fan-out applications. to ensure quick product migration, the non-transparency features are implemented in the same fashion as in standard pci applications. non-transparent bridges allow systems to isolate memory domains by presenting the processor subsystem as an endpoint, rath er than another me mory system. base address registers are used to translate addr esses; doorbell registers are used to send interrupts between the address domains; a nd scratchpad registers are accessible from both address domains to allow inter-processor communication. two virtual channels the expresslane pex 8524v switch supports 2 full-featured virtual channels (vcs) and a full 8 traffic classes (tcs). the mapping of traffic classes to port- specific virtual channels allows for diff erent mappings for different ports. in addition, the devices offer user-selectable virtual channel arbitration algorithms to enable users to fine tune the quality of service (qos) required for a specific application. low power with granular serdes control the pex 8524v provides low power capability that is fully compliant with the pci express power management specification. in addition, the serdes physical links can be turned off when unused for even lower power. pex 8524v version 1.4 2007 not recommended for new designs
flexible port width configuration the lane width for each port can be individually configured through auto-negotiation, hardware strapping, upstream software configuration, or through an optional eeprom. the pex 8524v supports a large number of port configurations. for example, if you are using the pex 8524v in a fan-out application, you may configure the upstream port as x8 and the downstream ports as four x4 ports; two x8 ports for dual-graphics fan-out; or other combinations, as long as you don?t run out of lanes (24) or ports (6). in a peer-to-peer application you can configure all six ports as x4. figure 1 shows the most common port configurations. figure 1. common port configurations hot plug for high availability hot plug capability allows users to replace hardware modules and perform maintenance without powering down the system. the pex 8524v hot plug capability and advanced error reporting features makes it suitable for high availability (ha) applications . each downstream port includes a standard hot plug controller. if the pex 8524v is used in an application where one or more of its downstream ports connect to pci express slots, each port?s hot plug controller can be used to manage the hot-plug event of its associated slot. furthermore, its upstream port is a hot-plug client , allowing it to be used on hot-pluggable adapter cards, backplanes, and fabric modules . fully compliant power management for applications that requir e power management, the pex 8524v device supports both link (l0, l0s, l1, l2/l3 ready, and l3) and device (d0 and d3hot) power management states, in compliance with the pci express power management specification. serdes power and signal management the expresslane pex 8524v supports software contr ol of the serdes outputs to allow optimization of power and signal strength in a system. the plx serdes implementation supports four levels of power ? off, low, typical, and high. the serdes block also supports loop-back modes and advanced reporting of error conditions , which enables efficient debug and management of the entire system. flexible virtual channel arbitration the expresslane pex 8524v switches support hardware fixed and round robin arbitration schemes for two virtual channels on each port. this allows for the fine tuning of quality of service for efficient use of packet buffers and system bandwidth. applications suitable for host-centric as well as peer-to-peer traffic patterns, the pex 8524v can be configured for a wide variety of form factors and applications. host-centric fan-out the pex 8524v, with its symme tric or asymmetric lane configuration capability, allows user specific tuning to a variety of host-centric applications. figure 2. fan-in/out usage figure 2 shows a typical server-based design, where the root complex provides a pci express link that needs to be fanned into a larger number of smaller ports for a variety of i/o functions, each with differen t bandwidth requirements. in this example, the pex 8524v would typically have an 8- lane upstream port, and as many as 5 downstream ports (4 shown here). the downstream ports can be of differing widths if required. the figure also shows how some of the ports can be bridged to provide pci or pci-x slots through the use of the expresslane pex 8114 and pex 8111 pcie bridging devices. not recommended for new designs
almost all (non x86 based) high-end microprocessor manufacturers are offering pci express interfaces. the pex 8524v can be directly connected to a processor to fan-out its pcie port to a larger number of ports for enhanced connectivity as illustrated in figure 3. figure 3. fan out for powerpc/mips cpus embedded systems the pex 8524v can also be utilized in embedded applications. figure 4 shows several independent modules connecting through the pex 8524v. the port widths for each module can be configured as required. the peer-to-peer communication feature of the pex 8524v allows these modules to communicate with each other without any centralized control. figure 4. embedded systems peer to peer communication figure 5 represents a backplane where the expresslane pex 8524v provides peer-to-peer data exchange for a large number of line cards where the cpu/host plays the management role. figure 5. peer-to-peer usage graphics fan-out switch as pcie based graphics cards become more mainstream, it will be necessary to take a x8 port on the root complex device and fan it out to two x8 ports for dual graphics applications. root complex (northbridge) devices are available with multiple pcie ports. these ports can be further expanded to connect to a larger number of i/os or to support dual-graphics using the pex 8524v as shown in figure 6. figure 6. graphics fan-out pci express port expansion the pex 8524v enables designers to take, for example, two x8 pcie ports and expand them into ten ports. some of these pcie ports can be bridged to pci or pci-x using bridging products from plx. figure 7 illustrates one of the many configurations the pex 8524v can support. figure 7. pcie port expansion not recommended for new designs
software usage model from a system model viewpoint, each pci express port is a virtual pci to pci bridge device and has its own set of pci express configuration registers. it is through the upstream port that the bios or host can configure the other ports using standard pci enumeration. the virtual pci to pci bridges within the pex 8524v are compliant to the pci and pci express system models. the configuration space registers (csrs) in a virtual primary/secondary pci to pci bridge are accessible by type 0 configurati on cycles through the virtual primary bus interface (matching bus number, device number, and function number). interrupt sources/events the expresslane pex 8524v switch supports the intx interrupt message type (compatible with pci 2.3 interrupt signals) or message signaled interrupts (msi) when enabled. interrupts/messages are generated by pex 8524v for hot plug events, doorbell interrupts, baseline error reporting, and advanced error reporting. development tools plx offers hardware and software tools to enable rapid customer design activity. these tools consist of a hardware module (pex 8524v rdk), hardware documentation, and a software development kit (sdk). figure 8. pex 8524v rdk expresslane pex 8524v rdk the rdk hardware module includes the pex 8524v with one x8 upstream port, one x8 downstream port, and two x4 downstream ports. the upstream port uses a x16 pci express edge connector. plx offers adapters (x8, x4, and x1) which can be used to plug the rdk in smaller slots. the pex 8524v rdk hardware module can be installed on a motherboard, used as a riser card, or configured as a bench-top board. the pex 8524v rdk can be used to test and validate customer software. additionally, it can be used as an evaluation vehicle for pex 8524v features and benefits. sdk the sdk tool set includes: - linux & windows drivers - c/c++ source code, objects, libraries - user?s guides & application examples plx technology, inc. 870 maude ave. sunnyvale, ca 94085 usa tel: 1-800-759-3735 tel: 1-408-774-9060 fax: 1-408-774-2169 email: info@plxtech.com web site: www.plxtech.com product ordering information part number description pex8524v-bb25bi 24-lane, 6-port pcie switch, 680-ball pbga 35x35mm 2 package pex8524v-bb25bi g 24-lane, 6-port pcie switch, 680-ball pbga 35x35mm 2 package, pb-free pex 8524v rdk-8 pex 8524v rapid development kit with x16 edge connector & x8 adapter pex 8524v rdk-4 pex 8524v rapid development kit with x16 edge connector & x4 adapter pex 8524v rdk-1 pex 8524v rapid development kit with x16 edge connector & x1 adapter please visit the plx web site at http://www.plxtech.com or contact plx sales at 408-774-9060 for samplin g . ? 2006 plx technology, inc. all rights reserved. plx and the plx l ogo are registered trademarks of plx technology, inc. express lane is a trademark of plx technology, inc., which may be registered in some juri sdiction. all other product names that appear in this material are for identification purposes only and are acknowledged to be trademarks or registered trademarks of th eir respective companies. information supplied by plx is believed to be accurate and r eliable, but plx technology, inc. assumes no responsibility for any errors that may appear in this material. plx technology, inc. reserves the right, without notice, to mak e changes in product design or specification. pex8524v-sil-pb-p1-1.4 01/07 not recommended for new designs
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